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d a t a sh eet product speci?cation supersedes data of 1996 dec 04 file under integrated circuits, ic03 1997 sep 03 integrated circuits tea1062; TEA1062A low voltage transmission circuits with dialler interface
1997 sep 03 2 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A features low dc line voltage; operates down to 1.6 v (excluding polarity guard) voltage regulator with adjustable static resistance provides a supply for external circuits symmetrical high-impedance inputs (64 k w ) for dynamic, magnetic or piezoelectric microphones asymmetrical high-impedance input (32 k w ) for electret microphones dtmf signal input with confidence tone mute input for pulse or dtmf dialling C tea1062: active high (mute) C TEA1062A: active low ( mute) receiving amplifier for dynamic, magnetic or piezoelectric earpieces large gain setting ranges on microphone and earpiece amplifiers line loss compensation (line current dependent) for microphone and earpiece amplifiers gain control curve adaptable to exchange supply dc line voltage adjustment facility. general description the tea1062 and TEA1062A are integrated circuits that perform all speech and line interface functions required in fully electronic telephone sets. they perform electronic switching between dialling and speech. the ics operate at line voltage down to 1.6 v dc (with reduced performance) to facilitate the use of more telephone sets connected in parallel. all statements and values refer to all versions unless otherwise specified. quick reference data symbol parameter conditions min. typ. max. unit v ln line voltage i line = 15 ma 3.55 4.0 4.25 v i line operating line current normal operation 11 - 140 ma with reduced performance 1 - 11 ma i cc internal supply current v cc = 2.8 v - 0.9 1.35 ma v cc supply voltage for peripherals i line =15ma tea1062 i p = 1.2 ma; mute = high 2.2 2.7 - v i p = 0 ma; mute = high - 3.4 - v TEA1062A i p = 1.2 ma; mute = low 2.2 2.7 - v i p = 0 ma; mute = low - 3.4 - v g v voltage gain microphone ampli?er 44 - 52 db receiving amplifier 20 - 31 db t amb operating ambient temperature - 25 - +75 c line loss compensation d g v gain control - 5.8 - db v exch exchange supply voltage 36 - 60 v r exch exchange feeding bridge resistance 0.4 - 1k w
1997 sep 03 3 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A ordering information block diagram type number package name description version tea1062 dip16 plastic dual in-line package; 16 leads (300 mil) sot38-1 tea1062m1 dip16 plastic dual in-line package; 16 leads (300 mil) sot38-4 or sot38-9 TEA1062A dip16 plastic dual in-line package; 16 leads (300 mil) sot38-1 TEA1062Am1 dip16 plastic dual in-line package; 16 leads (300 mil) sot38-4 or sot38-9 tea1062t so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 TEA1062At so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 fig.1 block diagram for TEA1062A. (1) pin 12 is active high (mute) for tea1062. handbook, full pagewidth mba359 - 1 slpe stab agc reg v ee gas2 gas1 v cc ln ir mic mic dtmf mute TEA1062A gar qr supply and reference db current reference control current low voltage circuit 10 7 6 11 12 91415 8 16 3 2 4 5 1 13 (1)
1997 sep 03 4 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A pinning note 1. pin 12 is active high (mute) for tea1062. symbol pin description ln 1 positive line terminal gas1 2 gain adjustment; transmitting ampli?er gas2 3 gain adjustment; transmitting ampli?er qr 4 non-inverting output; receiving ampli?er gar 5 gain adjustment; receiving ampli?er mic - 6 inverting microphone input mic+ 7 non-inverting microphone input stab 8 current stabilizer v ee 9 negative line terminal ir 10 receiving ampli?er input dtmf 11 dual-tone multi-frequency input mute 12 mute input (see note 1) v cc 13 positive supply decoupling reg 14 voltage regulator decoupling agc 15 automatic gain control input slpe 16 slope (dc resistance) adjustment fig.2 pin configuration for TEA1062A. handbook, halfpage mba354 - 1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TEA1062A ln gas1 gas2 qr gar stab slpe agc reg v cc mute dtmf ir v ee mic mic
1997 sep 03 5 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A functional description supplies v cc , ln, slpe, reg and stab power for the ic and its peripheral circuits is usually obtained from the telephone line. the supply voltage is derived from the line via a dropping resistor and regulated by the ic. the supply voltage v cc may also be used to supply external circuits e.g. dialling and control circuits. decoupling of the supply voltage is performed by a capacitor between v cc and v ee . the internal voltage regulator is decoupled by a capacitor between reg and v ee . the dc current flowing into the set is determined by the exchange supply voltage v exch , the feeding bridge resistance r exch and the dc resistance of the telephone line r line . the circuit has an internal current stabilizer operating at a level determined by a 3.6 k w resistor connected between stab and v ee (see fig.9). when the line current (i line ) is more than 0.5 ma greater than the sum of the ic supply current (i cc ) and the current drawn by the peripheral circuitry connected to v cc (i p ) the excess current is shunted to v ee via ln. the regulated voltage on the line terminal (v ln ) can be calculated as: v ln =v ref +i slpe r9 v ln =v ref + {(i line - i cc - 0.5 10 - 3 a) - i p } r9 v ref is an internally generated temperature compensated reference voltage of 3.7 v and r9 is an external resistor connected between slpe and v ee . in normal use the value of r9 would be 20 w . changing the value of r9 will also affect microphone gain, dtmf gain, gain control characteristics, sidetone level, maximum output swing on ln and the dc characteristics (especially at the lower voltages). under normal conditions, when i slpe >> i cc + 0.5 ma + i p , the static behaviour of the circuit is that of a 3.7 v regulator diode with an internal resistance equal to that of r9. in the audio frequency range the dynamic impedance is largely determined by r1. fig.3 shows the equivalent impedance of the circuit. at line currents below 9 ma the internal reference voltage is automatically adjusted to a lower value (typically 1.6 v at 1 ma). this means that more sets can be operated in parallel with dc line voltages (excluding the polarity guard) down to an absolute minimum voltage of 1.6 v. at line currents below 9 ma the circuit has limited sending and receiving levels. the internal reference voltage can be adjusted by means of an external resistor (r va ). this resistor when connected between ln and reg will decrease the internal reference voltage and when connected between reg and slpe will increase the internal reference voltage. current (i p ) available from v cc for peripheral circuits depends on the external components used. fig.10 shows this current for v cc > 2.2 v. if mute is low (tea1062) or mute is high (TEA1062A) when the receiving amplifier is driven, the available current is further reduced. current availability can be increased by connecting the supply ic (tea1081) in parallel with r1 as shown in fig.19 and fig.20, or by increasing the dc line voltage by means of an external resistor (r va ) connected between reg and slpe (fig.18). fig.3 equivalent impedance circuit. l eq =c3 r9 r p . r p = 16.2 k w . handbook, halfpage reg v ee v cc ln mba454 l eq r p r1 v ref r9 20 w c3 4.7 m f c1 100 m f
1997 sep 03 6 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A microphone inputs mic+ and mic - and gain pins gas1 and gas2 the circuit has symmetrical microphone inputs. its input impedance is 64 k w (2 32 k w ) and its voltage gain is typically 52 db (when r7 = 68 k w , see figures 14 and 15). dynamic, magnetic, piezoelectric or electret (with built-in fet source followers) can be used. microphone arrangements are illustrated in fig.11. the gain of the microphone amplifier can be adjusted between 44 db and 52 db to suit the sensitivity of the transducer in use. the gain is proportional to the value of r7 which is connected between gas1 and gas2. stability is ensured by two external capacitors, c6 connected between gas1 and slpe and c8 connected between gas1 and v ee . the value of c6 is 100 pf but this may be increased to obtain a first-order low-pass filter. the value of c8 is 10 times the value of c6. the cut-off frequency corresponds to the time constant r7 c6. input mute (tea1062) when mute is high the dtmf input is enabled and the microphone and receiving amplifier inputs are inhibited. the reverse is true when mute is low or open-circuit. mute switching causes only negligible clicking on the line and earpiece output. if the number of parallel sets in use causes a drop in line current to below 6 ma the speech amplifiers remain active independent to the dc level applied to the mute input. input mute (TEA1062A) when mute is low or open-circuit, the dtmf input is enabled and the microphone and receiving amplifier inputs are inhibited. the reverse is true when mute is high. mute switching causes only negligible clicking on the line and earpiece output. if the number of parallel sets in use causes a drop in line current to below 6 ma the dtmf amplifier becomes active independent to the dc level applied to the mute input. dual-tone multi-frequency input dtmf when the dtmf input is enabled dialling tones may be sent on to the line. the voltage gain from dtmf to ln is typically 25.5 db (when r7 = 68 k w ) and varies with r7 in the same way as the microphone gain. the signalling tones can be heard in the earpiece at a low level (confidence tone). receiving ampli?er ir, qr and gar the receiving amplifier has one input (ir) and a non-inverting output (qr). earpiece arrangements are illustrated in fig.12. the ir to qr gain is typically 31 db (when r4 = 100 k w ). it can be adjusted between 20 and 31 db to match the sensitivity of the transducer in use. the gain is set with the value of r4 which is connected between gar and qr. the overall receive gain, between ln and qr, is calculated by subtracting the anti-sidetone network attenuation (32 db) from the amplifier gain. two external capacitors, c4 and c7, ensure stability. c4 is normally 100 pf and c7 is 10 times the value of c4. the value of c4 may be increased to obtain a first-order low-pass filter. the cut-off frequency will depend on the time constant r4 c4. the output voltage of the receiving amplifier is specified for continuous-wave drive. the maximum output voltage will be higher under speech conditions where the peak to rms ratio is higher. automatic gain control input agc automatic line loss compensation is achieved by connecting a resistor (r6) between agc and v ee . the automatic gain control varies the gain of the microphone amplifier and the receiving amplifier in accordance with the dc line current. the control range is 5.8 db which corresponds to a line length of 5 km for a 0.5 mm diameter twisted-pair copper cable with a dc resistance of 176 w /km and average attenuation of 1.2 db/km). resistor r6 should be chosen in accordance with the exchange supply voltage and its feeding bridge resistance (see fig.13 and table 1). the ratio of start and stop currents of the agc curve is independent of the value of r6. if no automatic line-loss compensation is required the agc pin may be left open-circuit. the amplifiers, in this condition, will give their maximum specified gain.
1997 sep 03 7 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A sidetone suppression the anti-sidetone network, r1//z line , r2, r3, r8, r9 and z bal , (see fig.4) suppresses the transmitted signal in the earpiece. maximum compensation is obtained when the following conditions are fulfilled: (1) (2) if fixed values are chosen for r1, r2, r3 and r9, then condition (1) will always be fulfilled when | r8//z bal | << r3. to obtain optimum sidetone suppression, condition (2) has to be fulfilled which results in: where k is a scale factor; the scale factor k, dependent on the value of r8, is chosen to meet the following criteria: compatibility with a standard capacitor from the e6 or e12 range for z bal ? z bal //r8 ? << r3 fulfilling condition (a) and thus ensuring correct anti-sidetone bridge operation ? z bal + r8 ? >> r9 to avoid influencing the transmit gain. in practise z line varies considerably with the line type and length. the value chosen for z bal should therefore be for an average line length thus giving optimum setting for short or long lines. r9 r2 r1 r3 r8 z bal r8 z bal + ------------------------ - + ? ? ?? = z bal z bal r8 + ------------------------ - z line z line r1 + ------------------------- - = z bal r8 r1 ------- - z line kz line = = k r8 r1 ------- - = e xample the balance impedance z bal at which the optimum suppression is present can be calculated by: suppose z line = 210 w + (1265 w //140 nf) representing a 5 km line of 0.5 mm diameter, copper, twisted-pair cable matched to 600 w (176 w /km; 38 nf/km). when k = 0.64 then r8 = 390 w ; z bal = 130 w + (820 w //220 nf). the anti-sidetone network for the tea1060 family shown in fig.4 attenuates the signal received from the line by 32 db before it enters the receiving amplifier. the attenuation is almost constant over the whole audio-frequency range. figure 5 shows a conventional wheatstone bridge anti-sidetone circuit that can be used as an alternative. both bridge types can be used with either resistive or complex set impedances. (more information on the balancing of anti-sidetone bridges can be obtained in our publication applications handbook for wired telecom systems, ic03b , order number 9397 750 00811.)
1997 sep 03 8 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A fig.4 equivalent circuit of tea1060 family anti-sidetone bridge. handbook, full pagewidth msa500 - 1 ir r3 r8 slpe r9 z line v ee z bal i m r t r1 r2 ln fig.5 equivalent circuit of an anti-sidetone network in a wheatstone bridge configuration. bo ok, full pagewidth msa501 - 1 ir r8 slpe r9 r1 ln z line v ee z bal r a i m r t
1997 sep 03 9 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. mostly dependent on the maximum required t amb and on the voltage between ln and slpe (see figs 6, 7 and 8). 2. calculated for the maximum ambient temperature specified (t amb =75 c) and a maximum junction temperature of 125 c. handling this device meets class 2 esd test requirements [human body model (hbm)], in accordance with mil std 883c - method 3015 . thermal characteristics note 1. mounted on glass epoxy board 28.5 19.1 1.5 mm. symbol parameter conditions min. max. unit v ln positive continuous line voltage - 12 v v ln(r) repetitive line voltage during switch-on or line interruption - 13.2 v v ln(rm) repetitive peak line voltage for a 1 ms pulse per 5 s r9 = 20 w ; r10 = 13 w ; see fig.18 - 28 v i line line current r9 = 20 w ; note 1 - 140 ma v i input voltage on all other pins positive input voltage - v cc + 0.7 v negative input voltage -- 0.7 v p tot total power dissipation r9 = 20 w ; note 2 tea1062; TEA1062A - 666 mw tea1062m1; TEA1062Am1 - 617 mw tea1062t; TEA1062At - 454 mw t amb operating ambient temperature - 25 +75 c t stg storage temperature - 40 +125 c t j junction temperature - 125 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air tea1062; TEA1062A 75 k/w tea1062m1; TEA1062Am1 81 k/w tea1062t; TEA1062At (note 1) 110 k/w
1997 sep 03 10 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A fig.6 tea1062 and TEA1062A safe operating area. (1) t amb =45 c; p tot = 1068 mw. (2) t amb =55 c; p tot = 934 mw. (3) t amb =65 c; p tot = 800 mw. (4) t amb =75 c; p tot = 666 mw. handbook, halfpage 212 150 30 70 110 mlc200 46810 130 90 50 i ln (ma) v ln v slpe (v) (1) (2) (3) (4) fig.7 tea1062m1 and TEA1062Am1 safe operating area. (1) t amb =45 c; p tot = 988 mw. (2) t amb =55 c; p tot = 864 mw. (3) t amb =65 c; p tot = 741 mw. (4) t amb =75 c; p tot = 617 mw. handbook, halfpage 212 150 30 70 110 mlc201 46810 130 90 50 i ln (ma) v ln v slpe (v) (1) (2) (3) (4) fig.8 tea1062t and TEA1062At safe operating area. (1) t amb =45 c; p tot = 727 mw. (2) t amb =55 c; p tot = 636 mw. (3) t amb =65 c; p tot = 545 mw. (4) t amb =75 c; p tot = 454 mw. handbook, halfpage 212 150 30 70 110 mlc202 46810 130 90 50 i ln (ma) v ln v slpe (v) (1) (2) (3) (4)
1997 sep 03 11 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A characteristics i line = 11 to 140 ma; v ee = 0 v; f = 800 hz; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies ln and v cc (pins 1 and 13) v ln voltage drop over circuit between ln and v ee mic inputs open-circuit i line =1ma - 1.6 - v i line =4ma - 1.9 - v i line = 15 ma 3.55 4.0 4.25 v i line = 100 ma 4.9 5.7 6.5 v i line = 140 ma -- 7.5 v d v ln / d t variation with temperature i line =15ma -- 0.3 - mv/k v ln voltage drop over circuit between ln and v ee with external resistor r va i line =15ma r va (ln to reg) = 68 k w- 3.5 - v r va (reg to slpe) = 39 k w- 4.5 - v i cc supply current v cc = 2.8 v - 0.9 1.35 ma v cc supply voltage available for peripheral circuitry i line = 15 ma; mute = high tea1062 i p = 1.2 ma 2.2 2.7 - v i p =0ma - 3.4 - v v cc supply voltage available for peripheral circuitry i line = 15 ma; mute = low TEA1062A i p = 1.2 ma 2.2 2.7 - v i p =0ma - 3.4 - v microphone inputs mic - and mic+ (pins 6 and 7) ? z i ? input impedance differential between mic - and mic+ - 64 - k w single-ended mic - or mic+ to v ee - 32 - k w cmrr common mode rejection ratio - 82 - db g v voltage gain mic+ or mic - to ln i line = 15 ma; r7 = 68 k w 50.5 52.0 53.5 db d g vf gain variation with frequency referenced to 800 hz f = 300 and 3400 hz - 0.2 - db d g vt gain variation with temperature referenced to 25 c without r6; i line = 50 ma; t amb = - 25 and +75 c - 0.2 - db dtmf input (pin 11) | z i | input impedance - 20.7 - k w g v voltage gain from dtmf to ln i line = 15 ma; r7 = 68 k w 24.0 25.5 27.0 db d g vf gain variation with frequency referenced to 800 hz f = 300 and 3400 hz - 0.2 - db d g vt gain variation with temperature referenced to 25 c i line = 50 ma; t amb = - 25 and +75 c - 0.2 - db
1997 sep 03 12 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A gain adjustment inputs gas1 and gas2 (pins 2 and 3) d g v transmitting ampli?er gain variation by adjustment of r7 between gas1 and gas2 - 8 - 0db sending ampli?er output ln (pin 1) v ln(rms) output voltage (rms value) thd = 10% i line =4ma - 0.8 - v i line = 15 ma 1.7 2.3 - v v no(rms) noise output voltage (rms value) i line = 15 ma; r7 = 68 k w ; 200 w between mic - and mic+; psophometrically weighted (p53 curve) -- 69 - dbmp receiving ampli?er input ir (pin 10) ? z i ? input impedance - 21 - k w receiving ampli?er output qr (pin 4) ? z o ? output impedance - 4 -w g v voltage gain from ir to qr i line = 15 ma; r l = 300 w (from pin 9 to pin 4) 29.5 31 32.5 db d g vf gain variation with frequency referenced to 800 hz f = 300 and 3400 hz - 0.2 - db d g vt gain variation with temperature referenced to 25 c without r6; i line = 50 ma; t amb = - 25 and +75 c - 0.2 - db v o(rms) output voltage (rms value) thd = 2%; sine wave drive; r4 = 100 k w ; i line =15ma; i p =0ma r l = 150 w 0.22 0.33 - v r l = 450 w 0.3 0.48 - v v o(rms) output voltage (rms value) thd = 10%; r4 = 100 k w ; r l = 150 w ; i line =4ma - 15 - mv v no(rms) noise output voltage (rms value) i line = 15 ma; r4 = 100 k w ; ir open-circuit psophometrically weighted (p53 curve); r l = 300 w - 50 -m v gain adjustment input gar (pin 5) d g v receiving ampli?er gain variation by adjustment of r4 between gar and qr - 11 - 0db mute input (pin 12) v ih high level input voltage 1.5 - v cc v v il low level input voltage -- 0.3 v i mute input current - 815 m a symbol parameter conditions min. typ. max. unit
1997 sep 03 13 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A reduction of gain d g v mic+ or mic - to ln tea1062 mute = high - 70 - db TEA1062A mute = low - 70 - db g v voltage gain from dtmf to qr r4 = 100 k w ; r l = 300 w tea1062 mute = high -- 17 - db TEA1062A mute = low -- 17 - db automatic gain control input agc (pin 15) d g v controlling the gain from ir to qr and the gain from mic+, mic - to ln r6 = 110 k w (between agc and v ee ) i line =70ma gain control range -- 5.8 - db i lineh highest line current for maximum gain - 23 - ma i linel lowest line current for minimum gain - 61 - ma symbol parameter conditions min. typ. max. unit fig.9 supply arrangement. handbook, full pagewidth mba357 - 1 slpe stab reg v ee v cc ln i line slpe i ac dc peripheral circuits c1 0.5 ma 0.5 ma slpe i r exch v exch r line r1 i cc i p c3 r5 r9 tea1062 TEA1062A
1997 sep 03 14 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A fig.10 typical current i p available from v cc for peripheral circuitry. handbook, halfpage 012 4 2.4 0 0.8 1.6 msa504 3 v cc (v) i p (ma) (1) (2) the supply possibilities can be increased by setting the voltage drop over the circuit v ln to a higher value by resistor r va connected between reg and slpe. v cc > 2.2 v; i line = 15 ma at v ln = 4 v; r1 = 620 w ; r9 = 20 w . (1) i p = 2.1 ma. is valid when the receiving amplifier is not driven or when mute = high (tea1062), mute = low (TEA1062A). (2) i p = 1.7 ma. is valid when mute = low (tea1062), mute = high (TEA1062A) and the receiving amplifier is driven; v o(rms) = 150 mv, r l = 150 w.
1997 sep 03 15 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A fig.11 alternative microphone arrangements. (1) resistor may be connected to reduce the terminating impedance. a ndbook, full pagewidth msa505 v ee v cc mic mic mic mic mic mic (1) (a) (b) (c) 13 6 7 9 7 6 7 6 (a) magnetic or dynamic microphone. (b) electret microphone. (c) piezoelectric microphone. fig.12 alternative receiver arrangements. (1) resistor may be connected to prevent distortion (inductive load). (2) resistor is required to increase the phase margin (capacitive load). h andbook, full pagewidth (1) msa506 (2) qr (a) (b) (c) 4 9 4 9 v ee qr v ee qr v ee 4 9 (a) dynamic earpiece. (b) magnetic earpiece. (c) piezoelectric earpiece.
1997 sep 03 16 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A table 1 values of resistor r6 for optimum line-loss compensation at various values of exchange supply voltage (v exch ) and exchange feeding bridge resistance (r exch ); r9 = 20 w . v exch (v) r6 (k w ) r exch = 400 w r exch = 600 w r exch = 800 w r exch = 1000 w 36 100 78.7 -- 48 140 110 93.1 82 60 -- 120 102 fig.13 variation of gain as a function of line current with r6 as a parameter. handbook, full pagewidth msa507 - 1 6 4 2 0 d g v (db) 140 120 100 80 60 40 20 0 78.7 k w 110 k w 140 k w r6 = i (ma) line r9 = 20 w.
1997 sep 03 17 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A fig.14 test circuit for defining tea1062 voltage gain of mic+, mic - and dtmf inputs. voltage gain is defined as g v =20log ? v o /v i ? . for measuring gain from mic+ and mic - the mute input should be low or open-circuit. for measuring the dtmf input, the mute input should be high. inputs not being tested should be open-circuit. handbook, full pagewidth i line msa508 r6 r5 3.6 k w r9 20 w 16 slpe stab agc reg v ee 914 8 15 gas2 gas1 2 3 r7 68 k w r4 100 k w c4 100 pf c7 1 nf c8 1 nf c6 100 pf 100 m f r l 600 w v o v cc 13 1 ln r1 620 w 10 to 140 ma 10 m f v i c1 100 m f v i 10 7 6 11 12 ir mic mic dtmf mute tea1062 qr gar 4 5 c3 4.7 m f
1997 sep 03 18 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A fig.15 test circuit for defining TEA1062A voltage gain of mic+, mic - and dtmf inputs. voltage gain is defined as g v =20log ? v o /v i ? . for measuring gain from mic+ and mic - the mute input should be high. for measuring the dtmf input, the mute input should be low or open-circuit. inputs not being tested should be open-circuit. handbook, full pagewidth i line mba355 r6 16 slpe stab agc reg v ee 9 14 8 15 gas2 gas1 2 3 c4 100 pf c7 1 nf c8 1 nf c6 100 pf r l v o v cc 13 1 ln r1 10 to 140 ma v i c1 v i 10 7 6 11 12 ir mic mic dtmf mute TEA1062A qr gar 4 5 r5 3.6 k w r9 20 w r7 68 k w r4 100 k w 100 m f 600 w 620 w 10 m f 100 m f c3 4.7 m f
1997 sep 03 19 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A fig.16 test circuit for defining tea1062 voltage gain of the receiving amplifier. voltage gain is defined as g v =20log ? v o /v i ? . handbook, full pagewidth msa509 r6 16 slpe stab agc reg v ee 914 8 15 gas2 gas1 2 3 r7 c8 1 nf c6 100 pf v cc 13 1 ln r1 i line 10 to 140 ma v i c1 10 7 6 11 12 ir mic mic dtmf mute tea1062 gar c4 100 pf c7 1 nf qr 4 5 v o c2 z l r5 3.6 k w r9 20 w r4 100 k w 100 m f 600 w 620 w 10 m f 100 m f c3 4.7 m f fig.17 test circuit for defining TEA1062A voltage gain of the receiving amplifier. voltage gain is defined as g v =20log ? v o /v i ? . handbook, full pagewidth mba356 r6 16 slpe stab agc reg v ee 914 8 15 gas2 gas1 2 3 r7 c8 1 nf c6 100 pf v cc 13 1 ln r1 i line 10 to 140 ma v i c1 10 7 6 11 12 ir mic mic dtmf mute TEA1062A gar c4 100 pf c7 1 nf qr 4 5 v o c2 z l r5 3.6 k w r9 20 w r4 100 k w 100 m f 600 w 620 w 10 m f 100 m f c3 4.7 m f
1997 sep 03 20 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A application information handbook, full pagewidth mba358 - 1 slpe stab agc reg v ee gas2 gas1 mic mic dtmf mute TEA1062A gar qr 16 2 314 15 8 9 c6 r7 100 pf r va (r ) 16 - 14 r5 3.6 k w r6 c3 4.7 m f c8 1 nf r9 20 w 6 7 c4 100 pf c7 1 nf 4 5 r3 3.92 k w r4 c2 10 c5 100 nf r2 130 k w bzx79 - c12 r8 390 w z bal r10 13 w bas11 (2x) bzw14 (2x) telephone line ir ln v cc r1 620 w 11 12 113 c1 100 m f from dial and control circuits (1) fig.18 typical application of TEA1062A, with piezoelectric earpiece and dtmf dialling. the diode bridge, the zener diode and r10 limit the current into, and the voltage across, the circuit during line transients. a different protection arrangement is required for pulse dialling or register recall. the dc line voltage can be set to a higher value by the resistor r va (reg to slpe). further application information can be found in our publication applications handbook for wired telecom systems, ic03b , order number 9397 750 00811. (1) pin 12 is active high (mute) for tea1062.
1997 sep 03 21 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A handbook, full pagewidth mlc203 telephone line cradle contact tea1062 ln v cc dtmf mute v ee v dd v ss m1 pcd3310 bsn254a dp/flo tone r1 620 w fig.19 typical simplified application of the tea1062. (a) dtmf pulse set with cmos bilingual dialling circuit pcd3310. the dashed line shows an optional flash (register recall by timed loop break). handbook, full pagewidth mlc204 telephone line cradle contact TEA1062A ln v cc dtmf mute v ee v dd v ss m1 pcd3310t bsn254a dp/flo tone r1 620 w fig.20 typical simplified application of the TEA1062A. (a) dtmf pulse set with cmos bilingual dialling circuit pcd3310t. the dashed line shows an optional flash (register recall by time d loop break).
1997 sep 03 22 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A package outlines unit a max. 1 2 b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot38-1 92-10-02 95-01-19 a min. a max. b max. w m e e 1 1.40 1.14 0.055 0.045 0.53 0.38 0.32 0.23 21.8 21.4 0.86 0.84 6.48 6.20 0.26 0.24 3.9 3.4 0.15 0.13 0.254 2.54 7.62 0.30 8.25 7.80 0.32 0.31 9.5 8.3 0.37 0.33 2.2 0.087 4.7 0.51 3.7 0.15 0.021 0.015 0.013 0.009 0.01 0.10 0.020 0.19 050g09 mo-001ae m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 16 1 9 8 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z dip16: plastic dual in-line package; 16 leads (300 mil); long body sot38-1
1997 sep 03 23 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A references outline version european projection issue date iec jedec eiaj sot38-4 92-11-17 95-01-14 m h c (e ) 1 m e a l seating plane a 1 w m b 1 b 2 e d a 2 z 16 1 9 8 e pin 1 index b 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. unit a max. 12 b 1 (1) (1) (1) b 2 cd e e m z h l mm dimensions (inch dimensions are derived from the original mm dimensions) a min. a max. b max. w m e e 1 1.73 1.30 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 3.60 3.05 0.254 2.54 7.62 8.25 7.80 10.0 8.3 0.76 4.2 0.51 3.2 inches 0.068 0.051 0.021 0.015 0.014 0.009 1.25 0.85 0.049 0.033 0.77 0.73 0.26 0.24 0.14 0.12 0.01 0.10 0.30 0.32 0.31 0.39 0.33 0.030 0.17 0.020 0.13 dip16: plastic dual in-line package; 16 leads (300 mil) sot38-4
1997 sep 03 24 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A references outline version european projection issue date iec jedec eiaj sot38-9 97-07-24 m h c m e a l seating plane w m e d a 2 a 1 b 1 b 2 z 16 1 9 8 e pin 1 index b 0 5 10 mm scale note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. unit a max. b 1 (1) (1) (1) b 2 cd e e m h z l mm dimensions (mm dimensions are derived from the original inch dimensions) a 1 min. a 2 max. b max. w m e e 1 1.65 1.40 0.51 0.41 0.36 0.20 19.30 18.80 6.45 6.24 3.81 2.92 0.254 2.54 7.62 8.23 7.62 9.40 8.38 0.76 4.32 0.38 3.56 inches 0.065 0.055 0.020 0.016 0.014 0.008 1.14 0.76 0.045 0.030 0.76 0.74 0.254 0.246 0.150 0.115 0.01 0.10 0.30 0.324 0.300 0.37 0.33 0.030 0.17 0.015 0.14 dip16: plastic dual in-line package; 16 leads (300 mil) sot38-9 (e 1 )
1997 sep 03 25 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.0 0.4 sot109-1 95-01-23 97-05-22 076e07s ms-012ac 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.050 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
1997 sep 03 26 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A soldering plastic dual in-line packages b y dip or wave the maximum permissible temperature of the solder is 260 c; this temperature must not be in contact with the joint for more than 5 s. the total contact time of successive solder waves must not exceed 5 s. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified storage maximum. if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply the soldering iron below the seating plane (or not more than 2 mm above it). if its temperature is below 300 c, it must not be in contact for more than 10 s; if between 300 and 400 c, for not more than 5 s. plastic small-outline packages b ywave during placement and before soldering, the component must be fixed with a droplet of adhesive. after curing the adhesive, the component can be soldered. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder bath is 10 s, if allowed to cool to less than 150 c within 6 s. typical dwell time is 4 s at 250 c. a modified wave soldering technique is recommended using two solder waves (dual-wave), in which a turbulent wave with high upward pressure is followed by a smooth laminar wave. using a mildly-activated flux eliminates the need for removal of corrosive residues in most applications. b y solder paste reflow reflow soldering requires the solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the substrate by screen printing, stencilling or pressure-syringe dispensing before device placement. several techniques exist for reflowing; for example, thermal conduction by heated belt, infrared, and vapour-phase reflow. dwell times vary between 50 and 300 s according to method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 min at 45 c. r epairing soldered joints ( by hand - held soldering iron or pulse - heated solder tool ) fix the component by first soldering two, diagonally opposite, end pins. apply the heating tool to the flat part of the pin only. contact time must be limited to 10 s at up to 300 c. when using proper tools, all other pins can be soldered in one operation within 2 to 5 s at between 270 and 320 c. (pulse-heated soldering is not recommended for so packages.) for pulse-heated solder tool (resistance) soldering of vso packages, solder is applied to the substrate by dipping or by an extra thick tin/lead plating before package placement.
1997 sep 03 27 philips semiconductors product speci?cation low voltage transmission circuits with dialler interface tea1062; TEA1062A definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - 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